Ping sweep is a part of :
The virtual memory basically stores the next segment of data to be executed on the ………….
To access the services of operating system, the interface is provided by the :
The binary address issued to data or instructions are called as :
The disadvantage of the EPROM chip is :
The duration between the read and the mfc signal is …………..
The decoded instruction is stored in ……….
When a DNS server accepts and uses incorrect information from a host that has no authority giving that information then it is called :
In a network, if P is the only packet being transmitted and there was no earlier transmission. Which of the following delays could be zero
Transmission data rate is decided by :
Network congestion occurs………….
…………. Is a function in router that allows dumping of invalid packet for a specific network instead of forwarding.
Wildcard domain names start with label :
When collection of various computers seems a single coherent system to it is called:
In OSI model, when data is sent from device A to device B, the 5th layer to receive data at B is :
The number of layers in Internet protocol stack is :
Communication between a computer and a keyboard involves …………transmission
The process of transforming ciphertext plaintext is known as :
Point out the correct statement
Memories that can be assessed only in a pre-defined sequence are:
TCP/IP model was developed ………….. the OST model.
The …………. Is the physical path over which a message travels.
A…………….. is a device that forward packets between networks by processing the routing information included in the packet.
The operation which is not considered a basic operation of relational algebra is :
Which of the following is true concerning systems information in an RDBMS
Which of the following is a component of a distributed DBMS
Multi-casting is a special type of :
Which of the following protocols is not routable
The time period in which there was a shift from an industrial economy to an economy based on the value of information is known as the :
What is the first stage in a typical four-stage CPU pipeline